The continuous increase in transistor density on a single die has enabled integration of more and more components in SoCs, such as multiple processors, memories, and so on. Although integration of tens of thousands of components has significantly improved the intrinsic computational power of SoCs, it has correspondingly increased the design complexity, adding to the well-known problem of design productivity gap. To meet time-to-design and time-to-market deadlines, industry has primarily shifted to the use of parameterized components which allow design reuse and configuration of parameters to optimize the system under design for different metrics (such as performance and power).
The design and optimization of component-based SoCs faces a major challenge. The “design space” of a component-based SoC is defined as the universe of all the possible combinations of component parameters, where one combination of component parameters represents a single “design point”. A designer has to explore the design space to identify the optimal set of parameters for all the components (referred to as the optimal design point) with respect to an objective function. The effectiveness of design space exploration is limited by the high dimensionality of the design space, and the typically long simulation times required to determine the metrics associated with individual design points. For example, if a multiprocessor system-on-chip (MPSoC) contains parameterizable processors (having associated parameters such as processor type, frequency, etc.), parameterizable memory elements (having associated parameters such as memory type, size, speed, etc.), parameterizable interconnect elements (having associated parameters such as bus width, etc.) and so on, then clearly the number of design points is very large. In such cases, it is typically infeasible to cycle-accurately simulate all the design points and search through them to find the optimal design.
There is a large body of work on computation/estimation of metrics such as performance, power and energy for SoCs. Some works are ad-hoc in nature because they are applicable to a single SoC architecture. Others are relatively systematic in the sense that they can estimate multiple metrics and are applicable to a number of architectures with various components. The following paragraphs report current approaches to this problem.
One approach proposes a system-level performance estimation method for MPSoCs where instruction-level traces of processors are transformed into coarse-grained system-level traces. These system-level traces are then replayed in a SystemC simulator for quick performance estimation.
Another approach proposes a hybrid simulation method where a target instruction set simulator and a native simulation on a host are combined to speed up the performance estimation.
The aforementioned estimation methods are tailored towards specific architectures, and hence are considered to be ad hoc in nature.
Another approach adopts a systematic methodology by distinguishing between application and architecture models. Application models generate coarse-grained traces which are utilized in the architecture models through trace-driven simulation for quick performance estimation.
Another approach targets both performance and power estimation through the combined use of pre-characterization of SoC components and transaction-level modelling of the SoC. This computes the power consumption of a component-based SoC using concurrent and synchronized execution of individual power simulators of its components.
Another approach attempts a systematic integration of component simulators at different levels of abstraction for estimation/computation of any metric. This approach focuses on the issues and requirements for seamless integration of simulators for their fully or semi-automated invocation. In this approach, a designer himself has to determine the execution order of the simulators and how many times each simulator should be executed for a given design space.
Another approach proposes a divide-and-conquer-based approach to explore the design space efficiently. This approach describes a system as a combination of sub-systems (or components) that do not depend on each other, and assigns the parameters of the design space to individual sub-systems accordingly. As such, the design space of the system is partitioned into non-overlapping sub-spaces. Each sub-space is explored to find a centroid design point based upon its performance goals (which are computed from the system-level performance goals). For exploration of a sub-space, performance models (such as simulators, analytical equations, etc.) are used to calculate the performance of all the design points in the sub-space. The centroids of each sub-space are combined to create the system design point that fulfils the system-level performance goals. In this approach, a designer cannot decompose a system into its components if changing the parameters of one component affects the performance of another component in the decomposition whose parameters are not changed. As a consequence, this approach can only model a system consisting of simple sub-systems.